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VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
16 years 6 months ago
Register Transfer Operation Analysis during Data Path Verification
A control part ? data path partition based sequential circuit verification scheme aimed at avoiding state explosion comprises two major modules namely, a data path verifier and a ...
D. Sarkar
ICCAD
2009
IEEE
133views Hardware» more  ICCAD 2009»
15 years 3 months ago
A parallel preconditioning strategy for efficient transistor-level circuit simulation
A parallel computing approach for large-scale SPICE-accurate circuit simulation is described that is based on a new preconditioned iterative solver. The preconditioner involves the...
Heidi Thornquist, Eric R. Keiter, Robert J. Hoekst...
DSD
2006
IEEE
113views Hardware» more  DSD 2006»
15 years 8 months ago
Cascade Scheme for Concurrent Errors Detection
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades f...
Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladi...
TCAD
2002
145views more  TCAD 2002»
15 years 5 months ago
Automatic generation of synthetic sequential benchmark circuits
The design of programmable logic architectures and supporting computer-aided design tools fundamentally requires both a good understanding of the combinatorial nature of netlist gr...
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
ICCAD
2003
IEEE
140views Hardware» more  ICCAD 2003»
15 years 11 months ago
Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics
As research begins to explore potential nanotechnologies for future post-CMOS integrated systems, modeling and simulation environments must be developed that can accommodate the c...
Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan