53 search results - page 1 / 11 » Circuit Synthesis of Clock Distribution Networks Based on No... |
134
Voted
ISCAS
1995
IEEE
15 years 11 months ago
1995
IEEE
209
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DAC
2008
ACM
16 years 8 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
195
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DAC
2009
ACM
16 years 2 days ago
2009
ACM
We present an unconventional clock distribution that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modu...
179
Voted
GLVLSI
2010
IEEE
16 years 15 days ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...