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MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
16 years 20 days ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
MICRO
2007
IEEE
184views Hardware» more  MICRO 2007»
16 years 20 days ago
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlk...
MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
16 years 20 days ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
MICRO
2007
IEEE
150views Hardware» more  MICRO 2007»
16 years 20 days ago
Leveraging 3D Technology for Improved Reliability
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
Niti Madan, Rajeev Balasubramonian
P2P
2007
IEEE
16 years 20 days ago
A Data Placement Scheme with Time-Related Model for P2P Storages
Maintaining desired data availability while minimizing costs is the primary challenge in designing P2P storages. Data placement schemes and data availability calculation methods a...
Jing Tian, Zhi Yang, Yafei Dai