56 search results - page 5 / 12 » Chip and PIN is Broken |
174
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
147
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ISCAS
2006
IEEE
16 years 1 days ago
2006
IEEE
Abstract—We describe a neuromorphic chip with a twolayer excitatory-inhibitory recurrent network of spiking neurons that exhibits localized clusters of neural activity. Unlike ot...
110
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ITC
2003
IEEE
15 years 11 months ago
2003
IEEE
Backside light emission and electrical measurements were used to evaluate the susceptibility to latchup of externally cabled I/O pins for a 0.13 µm technology generation [1,2] te...
142
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ISPD
1998
ACM
15 years 10 months ago
1998
ACM
In this paper, we present a performance-driven softmacro clustering and placement method which preserves HDL design hierarchy to guide the soft-macro placement process. We also pr...
157
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ASPDAC
2008
ACM
15 years 7 months ago
2008
ACM
Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in...