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DAC
2002
ACM
16 years 7 months ago
Design of a high-throughput low-power IS95 Viterbi decoder
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
Xun Liu, Marios C. Papaefthymiou
GLOBECOM
2006
IEEE
16 years 3 days ago
A Practical Switch-Memory-Switch Architecture Emulating PIFO OQ
— Emulating Output Queued (OQ) Switch with sustainable implementation cost and low fixed delay is always preferable in designing high performance routers. The SwitchMemory-Switch...
Nan Hua, Yang Xu, Peng Wang, Depeng Jin, Lieguang ...
171
Voted
IEEEPACT
2007
IEEE
16 years 11 days ago
Architectural Support for the Stream Execution Model on General-Purpose Processors
There has recently been much interest in stream processing, both in industry (e.g., Cell, NVIDIA G80, ATI R580) and academia (e.g., Stanford Merrimac, MIT RAW), with stream progra...
Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mende...
SPAA
2003
ACM
15 years 11 months ago
Novel architectures for P2P applications: the continuous-discrete approach
We propose a new approach for constructing P2P networks based on a dynamic decomposition of a continuous space into cells corresponding to servers. We demonstrate the power of thi...
Moni Naor, Udi Wieder
131
Voted
DAC
2009
ACM
16 years 7 months ago
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
This paper presents a technique to improve the storage density of spin-torque transfer (STT) magnetoresistive random access memory (MRAM) in the presence of significant magnetic t...
Wei Xu, Yiran Chen, Xiaobin Wang, Tong Zhang