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ASPDAC
2001
ACM
104views Hardware» more  ASPDAC 2001»
15 years 9 months ago
Optimal spacing and capacitance padding for general clock structures
Clock-tuning has been classified as important but tough tasks due to the non-convex nature caused by the skew requirements. As a result, all existing mathematical programming appr...
Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen
VLSID
2004
IEEE
73views VLSI» more  VLSID 2004»
16 years 6 months ago
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling
Reduction of worst-case delay and delay uncertainty due to capacitive coupling is a still unsolved problem in physical design. We describe a routing only layout solution - swizzli...
Puneet Gupta, Andrew B. Kahng
ESA
2007
Springer
115views Algorithms» more  ESA 2007»
16 years 3 days ago
Approximation of Partial Capacitated Vertex Cover
We study the partial capacitated vertex cover problem (pcvc) in which the input consists of a graph G and a covering requirement L. Each edge e in G is associated with a demand (o...
Reuven Bar-Yehuda, Guy Flysher, Julián Mest...
CIAC
2010
Springer
246views Algorithms» more  CIAC 2010»
15 years 9 months ago
Capacitated Confluent Flows: Complexity and Algorithms
A flow on a directed network is said to be confluent if the flow uses at most one outgoing arc at each node. Confluent flows arise naturally from destination-based routing. We stud...
Daniel Dressler and Martin Strehler
ISPD
1999
ACM
95views Hardware» more  ISPD 1999»
15 years 10 months ago
Incremental capacitance extraction and its application to iterative timing-driven detailed routing
In this paper, we consider delay optimization in multilayer detailed routing. Given a detailed routing by some detailed router, we iteratively improve the delays of critical nets ...
Yanhong Yuan, Prithviraj Banerjee