Sciweavers

4809 search results - page 713 / 962
» CajunBot: Architecture and algorithms
Sort
View
VLSI
2010
Springer
15 years 1 months ago
A design workflow for dynamically reconfigurable multi-FPGA systems
Multi-FPGA systems (MFS's) represent a promising technology for various applications, such as the implementation of supercomputers and parallel and computational intensive emu...
Alessandro Panella, Marco D. Santambrogio, Frances...

Publication
266views
15 years 56 min ago
NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision
In this paper we present a scalable dataflow hard- ware architecture optimized for the computation of general- purpose vision algorithms—neuFlow—and a dataflow compiler—luaFl...
C. Farabet, B. Martini, B. Corda, P. Akselrod, E. ...
CISS
2011
IEEE
14 years 10 months ago
The Restricted Isometry Property for block diagonal matrices
—In compressive sensing (CS), the Restricted Isometry Property (RIP) is a powerful condition on measurement operators which ensures robust recovery of sparse vectors is possible ...
Han Lun Yap, Armin Eftekhari, Michael B. Wakin, Ch...
332
Voted
CONIELECOMP
2011
IEEE
14 years 10 months ago
DSRP: Distributed SensorWeb Routing Protocol
—We propose a new multi-hop routing protocol for wireless sensor networks, suited for monitoring and control applications. The aim of this research is to adapt flat and hierarch...
Abhinav Valada, David Kohanbash, George Kantor
ICASSP
2011
IEEE
14 years 10 months ago
Efficient iterative receiver for bit-Interleaved Coded Modulation according to the DVB-T2 standard
Bit-Interleaved Coded Modulation (BICM) offers a significant improvement in error correcting performance for coded modulations over fading channels compared to the previously exis...
Meng Li, Charbel Abdel Nour, Christophe Jég...