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192
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VLSID
2002
IEEE
16 years 7 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
149
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VLSID
2002
IEEE
16 years 7 months ago
2002
IEEE
In floorplan design, it is common that a designer will want to control the positions of some modules in the final packing for various purposes like data path alignment, I/O connec...
219
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VLSID
2002
IEEE
16 years 7 months ago
2002
IEEE
In this paper, a new logic synthesis method for an AND-XOR-OR type sense-amplifying PLA is proposed. An AND-XOR-OR type sense-amplifying PLA can achieve lowpower dissipation and h...
283
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POPL
2001
ACM
16 years 7 months ago
2001
ACM
Secure Safe Ambients (SSA) are a typed variant of Safe Ambients [9], whose type system allows behavioral invariants of ambients to be expressed and verified. The most significant a...
170
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RECOMB
2008
Springer
16 years 7 months ago
2008
Springer
Abstract. As data about genomic architecture accumulates, genomic rearrangements have attracted increasing attention. One of the main rearrangement mechanisms, inversions (also cal...