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DATE
2004
IEEE
114views Hardware» more  DATE 2004»
15 years 10 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
EUROGP
2004
Springer
170views Optimization» more  EUROGP 2004»
15 years 10 months ago
Comparing Hybrid Systems to Design and Optimize Artificial Neural Networks
Abstract. In this paper we conduct a comparative study between hybrid methods to optimize multilayer perceptrons: a model that optimizes the architecture and initial weights of mul...
Pedro A. Castillo Valdivieso, Maribel Garcí...
DAC
1995
ACM
15 years 10 months ago
Register Allocation and Binding for Low Power
This paper describes a technique for calculating the switching activity of a set of registers shared by di erent data values. Based on the assumption that the joint pdf (probabili...
Jui-Ming Chang, Massoud Pedram
DAC
1995
ACM
15 years 10 months ago
A General Method for Compiling Event-Driven Simulations
Abstract—We present a new approach to event-driven simulation that does not use a centralized run-time event queue, yet is capable of handling arbitrary models, including those w...
Robert S. French, Monica S. Lam, Jeremy R. Levitt,...
156
Voted
DAC
1995
ACM
15 years 10 months ago
Code Optimization Techniques for Embedded DSP Microprocessors
—We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventiona...
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Stev...