Sciweavers

4809 search results - page 404 / 962
» CajunBot: Architecture and algorithms
Sort
View
DAC
2004
ACM
16 years 7 months ago
STAC: statistical timing analysis with correlation
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...
Jiayong Le, Xin Li, Lawrence T. Pileggi
DAC
2005
ACM
16 years 7 months ago
System-level energy-efficient dynamic task scheduling
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time...
Jianli Zhuo, Chaitali Chakrabarti
SIGSOFT
2009
ACM
16 years 7 months ago
Synthesizing partial component-level behavior models from system specifications
Initial system specifications, such as use-case scenarios and properties, only partially specify the future system. We posit that synthesizing partial component-level behavior mod...
Ivo Krka, Yuriy Brun, George Edwards, Nenad Medvid...
VLSID
2006
IEEE
240views VLSI» more  VLSID 2006»
16 years 7 months ago
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition
Logarithmic Number Systems (LNS) offer a viable alternative in terms of area, delay and power to binary number systems for multiplication and division operations in signal process...
Venkataraman Mahalingam, N. Ranganathan
ICCAD
2001
IEEE
91views Hardware» more  ICCAD 2001»
16 years 3 months ago
A System for Synthesizing Optimized FPGA Hardware from MATLAB
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
Malay Haldar, Anshuman Nayak, Alok N. Choudhary, P...