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DAC
2005
ACM
15 years 8 months ago
Multiplexer restructuring for FPGA implementation cost reduction
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
Paul Metzgen, Dominic Nancekievill
IJFCS
2006
82views more  IJFCS 2006»
15 years 6 months ago
Routing Multiple Width Communications on the Circuit Switched Tree
Dynamically reconfigurable architectures offer extremely fast solutions to various problems. The Circuit Switched Tree (CST) is an important interconnect used to implement such ar...
Krishnendu Roy, Ramachandran Vaidyanathan, Jerry L...
JSAT
2008
85views more  JSAT 2008»
15 years 6 months ago
Parallel SAT Solving using Bit-level Operations
We show how to exploit the 32/64 bit architecture of modern computers to accelerate some of the algorithms used in satisfiability solving by modifying assignments to variables in ...
Marijn Heule, Hans van Maaren
183
Voted
JNW
2006
145views more  JNW 2006»
15 years 6 months ago
A Comparison of Replication Strategies for Reliable Decentralised Storage
Distributed hash tables (DHTs) can be used as the basis of a resilient lookup service in unstable environments: local routing tables are updated to reflected changes in the network...
Matthew Leslie, Jim Davies, Todd Huffman
JCP
2007
94views more  JCP 2007»
15 years 6 months ago
Low-Complexity Analysis of Repetitive Regularities for Biometric Applications
— Presented in this paper is a joint algorithm optimization and architecture design framework for analysis of repetitive regularities. Two closely coupled algorithm optimization ...
Lei Wang, Niral Patel