Sciweavers

4809 search results - page 330 / 962
» CajunBot: Architecture and algorithms
Sort
View
DAC
2004
ACM
16 years 7 months ago
Synthesizing interconnect-efficient low density parity check codes
Error correcting codes are widely used in communication and storage applications. Codec complexity has usually been measured with a software implementation in mind. A recent hardw...
Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Way...
MOBIHOC
2009
ACM
16 years 7 months ago
Demonstration of highly programmable downlink OFDMA (WiMax) transceivers for SDR systems
In this paper, we present the architecture of a highly configurable multi-input multi?output (MIMO) orthogonal frequency division multiple access (OFDMA) platform. The platform is...
Hamid Eslami, Gaurav Patel, Chitaranjan P. Sukumar...
199
Voted
VLSID
2005
IEEE
123views VLSI» more  VLSID 2005»
16 years 7 months ago
Variance Reduction in Monte Carlo Capacitance Extraction
In this article we address efficiency issues in implementation of Monte Carlo algorithm for 3D capacitance extraction. Error bounds in statistical capacitance estimation are discus...
Shabbir H. Batterywala, Madhav P. Desai
VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
16 years 7 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
VLSID
2004
IEEE
181views VLSI» more  VLSID 2004»
16 years 7 months ago
Real Time Dynamic Voltage Scaling For Embedded Systems
This paper presents a very efficient and versatile method to handle Dynamic Voltage Scaling for minimizing energy consumption in an embedded system processor while maintaining rea...
Venkat Rao, Gaurav Singhal, Anshul Kumar