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ICASSP
2008
IEEE
16 years 1 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
ICRA
2008
IEEE
201views Robotics» more  ICRA 2008»
16 years 1 months ago
Hierarchical distributed control for search and tracking by heterogeneous aerial robot networks
Abstract—This paper presents a hierarchical control architecture that enables cooperative surveillance by a heterogeneous aerial robot network comprised of mothership unmanned ai...
Jack Elston, Eric W. Frew
NCA
2007
IEEE
16 years 1 months ago
Improving Network Processing Concurrency using TCPServers
Exponentially growing bandwidth requirements and slowing gains in processor speeds have led to the popularity of multiprocessor architectures. Network stack parallelism is increas...
Aniruddha Bohra, Liviu Iftode
NOCS
2007
IEEE
16 years 1 months ago
On the Design of a Photonic Network-on-Chip
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...
Assaf Shacham, Keren Bergman, Luca P. Carloni
241
Voted
ATAL
2007
Springer
16 years 28 days ago
A framework for agent-based distributed machine learning and data mining
This paper proposes a framework for agent-based distributed machine learning and data mining based on (i) the exchange of meta-level descriptions of individual learning processes ...
Jan Tozicka, Michael Rovatsos, Michal Pechoucek