Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tabl...
A Module-Rased design flow for digital ICs with hard and sofl modules is presented. Versions of the sofl modules are implemented with different areddelay characteristics. The vers...
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...
Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J....
We propose a fully-distributed peer-to-peer architecture to solve the scalability problem of Networked Virtual Environment in a simple and efficient manner. Our method exploits lo...
We present a new approach that is able to produce an increased fault tolerance in bio-inspired electronic circuits. To this end, we designed hardwarefriendly genetic regulatory net...