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SI3D
1995
ACM
15 years 10 months ago
The Sort-First Rendering Architecture for High-Performance Graphics
Interactive graphics applications have long been challenging graphics system designers by demanding machines that can provide ever increasing polygon rendering performance. Anothe...
Carl Mueller
ASPDAC
2007
ACM
99views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...
Dan Zhao, Unni Chandran, Hideo Fujiwara
INTERWORKING
2000
15 years 10 months ago
Design of a Multi-layer Bandwidth Broker Architecture
Internet is widely known for lacking any kind of mechanism for the provisioning of Quality of Service guarantees. The Internet community concentrates its efforts on the Bandwidth ...
George A. Politis, Petros Sampatakos, Iakovos S. V...
ACIVS
2008
Springer
15 years 8 months ago
An Efficient Hardware Architecture without Line Memories for Morphological Image Processing
In this paper, we present a novel hardware architecture to achieve erosion and dilation with a large structuring element. We are proposing a modification of HGW algorithm with a bl...
Christophe Clienti, Michel Bilodeau, Serge Beucher
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures
Abstract-- We address performance maximization of independent task sets under energy constraint on chip multi-processor (CMP) architectures that support multiple voltage/frequency ...
Sushu Zhang, Karam S. Chatha