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CAV
2007
Springer
116views Hardware» more  CAV 2007»
16 years 24 days ago
A Decision Procedure for Bit-Vectors and Arrays
Abstract. STP is a decision procedure for the satisfiability of quantifier-free formulas in the theory of bit-vectors and arrays that has been optimized for large problems encoun...
Vijay Ganesh, David L. Dill
DAC
2006
ACM
16 years 17 days ago
High-performance operating system controlled memory compression
This article describes a new software-based on-line memory compression algorithm for embedded systems and presents a method of adaptively managing the uncompressed and compressed ...
Lei Yang, Haris Lekatsas, Robert P. Dick
ICASSP
2010
IEEE
15 years 4 months ago
A distributed psycho-visually motivated Canny edge detector
This paper proposes a distributed Canny edge detection algorithm which can be mapped onto multi-core architectures for high throughput applications. In contrast to the conventiona...
Srenivas Varadarajan, Chaitali Chakrabarti, Lina J...
MICRO
1997
IEEE
105views Hardware» more  MICRO 1997»
15 years 10 months ago
The Multicluster Architecture: Reducing Cycle Time Through Partitioning
The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of t...
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvon...
ICCAD
1994
IEEE
106views Hardware» more  ICCAD 1994»
15 years 10 months ago
On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution
Several industrial FPGA routing architectures have been shown to have no efficient routing algorithms (unless P=NP) [3,4]. Here, we further investigate if the intractability of th...
Yu-Liang Wu, Douglas Chang