––This paper describes algorithms for automatic layout synthesisofleafcellsin1–dandinanew1–1/2–dlayoutstyle,useful for non–dual circuit styles. The graph theory based a...
- Many memory-sensitive embedded applications can tolerate small performance degradations if doing so can reduce the memory space requirements significantly. This paper explores th...
The complexity and physical distribution of modern active-safety automotive applications requires the use of distributed architectures. These architectures consist of multiple ele...
Abhijit Davare, Qi Zhu, Marco Di Natale, Claudio P...
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
The increasing performance gap between processors and memory will force future architectures to devote significant resources towards removing and hiding memory latency. The two ma...