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IJNM
2008
103views more  IJNM 2008»
15 years 6 months ago
An efficient architecture for Bandwidth Brokers in DiffServ networks
In this article we examine the architecture of an entity used for automatic management and provisioning of resources for DiffServ networks. We examine the existing literature and ...
Christos Bouras, Kostas Stamos
187
Voted
NN
2008
Springer
153views Neural Networks» more  NN 2008»
15 years 6 months ago
A biologically motivated visual memory architecture for online learning of objects
We present a biologically motivated architecture for object recognition that is based on a hierarchical feature-detection model in combination with a memory architecture that impl...
Stephan Kirstein, Heiko Wersing, Edgar Körner
DATE
2005
IEEE
111views Hardware» more  DATE 2005»
15 years 8 months ago
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumptio
This paper proposes a novel architecture synthesis algorithm for single-loop single-bit ∆Σ modulators. We defined a generic modulator architecture and derived its noise and si...
Hua Tang, Ying Wei, Alex Doboli
ICCAD
1995
IEEE
106views Hardware» more  ICCAD 1995»
15 years 10 months ago
Re-engineering of timing constrained placements for regular architectures
In a typical design ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
Anmol Mathur, K. C. Chen, C. L. Liu
WOTUG
2007
15 years 7 months ago
C++CSP2: A Many-to-Many Threading Model for Multicore Architectures
Abstract. The advent of mass-market multicore processors provides exciting new opportunities for parallelism on the desktop. The original C++CSP – a library providing concurrency...
Neil Brown