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ASPDAC
2005
ACM
132views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Automatic synthesis and scheduling of multirate DSP algorithms
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousia...
DATE
2004
IEEE
105views Hardware» more  DATE 2004»
15 years 10 months ago
Time-Energy Design Space Exploration for Multi-Layer Memory Architectures
This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. Th...
Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuc...
EUROCRYPT
2000
Springer
15 years 10 months ago
Cox-Rower Architecture for Fast Parallel Montgomery Multiplication
Abstract. This paper proposes a fast parallel Montgomery multiplication algorithm based on Residue Number Systems (RNS). It is easy to construct a fast modular exponentiation by ap...
Shin-ichi Kawamura, Masanobu Koike, Fumihiko Sano,...
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
15 years 6 months ago
A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems
Multiple Input - Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix computations which are directly related to increased power and area consumpt...
Zahid Khan, Tughrul Arslan, John S. Thompson, Ahme...
INFOCOM
2005
IEEE
16 years 4 days ago
Low-state fairness: lower bounds and practical enforcement
— Providing approximate max-min fair bandwidth allocation among flows within a network or at a single router has been an important research problem. In this paper, we study the ...
Abhimanyu Das, Debojyoti Dutta, Ahmed Helmy, Ashis...