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VLSID
2007
IEEE
92views VLSI» more  VLSID 2007»
16 years 7 months ago
Floorplanning in Modern FPGAs
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
ICASSP
2009
IEEE
16 years 1 months ago
Cross-layer optimization of wireless fading ad-hoc networks
This paper introduces an algorithm to approximately find optimal wireless networks in presence of fading. Joint optimization of application level rates, routes, link capacities, ...
Nikolaos Gatsis, Alejandro Ribeiro, Georgios B. Gi...
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
16 years 24 days ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
ICMCS
2005
IEEE
114views Multimedia» more  ICMCS 2005»
16 years 4 days ago
Decentralized periodic broadcasting for large-scale video streaming
Periodic broadcasting (PB) schemes are the most promising solution for building large-scale video streaming services. Existing PB schemes are all built around the traditional clie...
Ka Ki To, Jack Y. B. Lee, S.-H. Gary Chan
ISCAS
2005
IEEE
99views Hardware» more  ISCAS 2005»
16 years 3 days ago
On the implementation of 128-pt FFT/IFFT for high-performance WPAN
- This paper deals with the efficient realization of a 128-pt FFT/IFFT processor for application in IEEE 802.15.3a standard. The 128-pt FFT/IFFT architecture has been designed by d...
C. Huggett, K. Maharatna, K. Paul