Sciweavers

4809 search results - page 173 / 962
» CajunBot: Architecture and algorithms
Sort
View
ASPDAC
2010
ACM
163views Hardware» more  ASPDAC 2010»
15 years 4 months ago
A3MAP: architecture-aware analytic mapping for networks-on-chip
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...
Wooyoung Jang, David Z. Pan
DAC
2005
ACM
16 years 7 months ago
Incremental retiming for FPGA physical synthesis
In this paper, we present a new linear-time retiming algorithm that produces near-optimal results. Our implementation is specifically targeted at Altera's Stratix [1] FPGAbas...
Deshanand P. Singh, Valavan Manohararajah, Stephen...
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
16 years 17 days ago
ASIP design and synthesis for non linear filtering in image processing
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
Luca Fanucci, Michele Cassiano, Sergio Saponara, D...
IPPS
1999
IEEE
15 years 10 months ago
Experimental Evaluation of QSM, a Simple Shared-Memory Model
Parallel programming models should attempt to satisfy two conflicting goals. On one hand, they should hide architectural details so that algorithm designers can write simple, port...
Brian Grayson, Michael Dahlin, Vijaya Ramachandran
ICC
2007
IEEE
102views Communications» more  ICC 2007»
16 years 25 days ago
Frequency Domain Joint Estimation of Synchronization Parameter and Channel Impulse Response in Composite Radio Receiver
— In this paper, an innovative frequency domain joint estimation algorithm of synchronization parameter and channel impulse response (CIR) in Direct Sequence Code Division Multip...
Tianqi Wang, Cheng Li, Hsiao-Hwa Chen