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SBCCI
2004
ACM
111views VLSI» more  SBCCI 2004»
15 years 12 months ago
A partial reconfigurable architecture for controllers based on Petri nets
Digital Control System in the industry has been used in most of the applications based on expensive Programmable Logical Controllers (PLC). These Systems are, in general, highly c...
Paulo Sérgio B. do Nascimento, Paulo Romero...
DFT
2003
IEEE
64views VLSI» more  DFT 2003»
15 years 11 months ago
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
DSN
2003
IEEE
15 years 11 months ago
Evaluation of Fault Handling of the Time-Triggered Architecture with Bus and Star Topology
Arbitrary faults of a single node in a time-triggered architecture (TTA) bus topology system may cause error propagation to correct nodes and may lead to inconsistent system state...
Astrit Ademaj, Håkan Sivencrona, Günthe...
DSRT
2003
IEEE
15 years 11 months ago
An Agent Architecture for Network Support of Distributed Simulation Systems
Continued research into distributed agent-based systems and evolving web based technologies are opening up tremendous possibilities for the deployment of large scale and highly ex...
Robert Simon, Woan Sun Chang, J. Mark Pullen
FCCM
2003
IEEE
113views VLSI» more  FCCM 2003»
15 years 11 months ago
Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development
Although domain-specialized FPGAs can offer significant area, speed and power improvements over conventional reconfigurable devices, there are several unique and unexplored design...
Kenneth Eguro, Scott Hauck