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GLVLSI
2009
IEEE
186views VLSI» more  GLVLSI 2009»
16 years 1 months ago
Bitmask-based control word compression for NISC architectures
Implementing a custom hardware is not always feasible due to cost and time considerations. No instruction set computer (NISC) architecture is one of the promising direction to des...
Chetan Murthy, Prabhat Mishra
GLOBECOM
2008
IEEE
16 years 26 days ago
Joint Channel and Mismatch Correction for OFDM Reception with Time-interleaved ADCs: Towards Mostly Digital MultiGigabit Transce
— Time-interleaved (TI) analog-to-digital converters (ADCs) are a promising architecture for realizing the highspeed ADCs required to implement “mostly digital” receivers for...
P. Sandeep, Upamanyu Madhow, Munkyo Seo, Mark J. W...
RTAS
2008
IEEE
16 years 24 days ago
Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures
Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues p...
Jack Whitham, Neil C. Audsley
BROADNETS
2007
IEEE
16 years 23 days ago
DATALITE: a distributed architecture for traffic analysis via light-weight traffic digest
-- In this paper, we propose DATALITE, a Distributed Architecture for Traffic Analysis via LIghtweight Traffic digEst, which introduces a set of new distributed algorithms and prot...
Wing Cheong Lau, Murali S. Kodialam, T. V. Lakshma...
ICC
2007
IEEE
138views Communications» more  ICC 2007»
16 years 22 days ago
Scalable Router Memory Architecture Based on Inter-leaved DRAM: Analysis and Numerical Studies
1  Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitabl...
Feng Wang, Mounir Hamdi