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    EURODAC
    1995
    IEEE
    134views VHDL» more  EURODAC 1995»
    Area efficient DSP datapath synthesis
    15 years 10 months ago
    Area efficient DSP datapath synthesis
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    Andrew A. Duncan, David C. Hendry
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    EURODAC
    1995
    IEEE
    155views VHDL» more  EURODAC 1995»
    Design and use of a system-level specification and verification methodology
    15 years 10 months ago
    Design and use of a system-level specification and verification methodology
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    M. M. Kamal Hashmi, Alistair C. Bruce
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    FCT
    1995
    Springer
    94views Applied Computing» more  FCT 1995»
    Discrete Time Process Algebra with Abstraction
    15 years 10 months ago
    Discrete Time Process Algebra with Abstraction
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    Jos C. M. Baeten, Jan A. Bergstra
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    FOCS
    1995
    IEEE
    101views Theoretical Computer Science» more  FOCS 1995»
    Minimum Coloring Random and Semi-Random Graphs in Polynomial Expected Time
    15 years 10 months ago
    Minimum Coloring Random and Semi-Random Graphs in Polynomial Expected Time
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    C. R. Subramanian
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    ICCD
    1995
    IEEE
    95views Hardware» more  ICCD 1995»
    Caching processor general registers
    15 years 10 months ago
    Caching processor general registers
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    Robert Yung, Neil C. Wilhelm
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