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TVLSI
2008
164views more  TVLSI 2008»
15 years 6 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
16 years 16 days ago
A Scalable FPGA-based Multiprocessor
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
Arun Patel, Christopher A. Madill, Manuel Salda&nt...
DATE
2009
IEEE
128views Hardware» more  DATE 2009»
16 years 1 months ago
A case study in distributed deployment of embedded software for camera networks
—We present an embedded software application for the real-time estimation of building occupancy using a network of video cameras. We analyze a series of alternative decomposition...
Francesco Leonardi, Alessandro Pinto, Luca P. Carl...
DAC
2004
ACM
16 years 7 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
RTSS
1996
IEEE
15 years 10 months ago
Middleware for Distributed Industrial Real-Time Systems on ATM Networks
In this paper we address the problem of middleware design for constructing ATM LAN based distributed industrial plant monitoring and control systems. In particular, we present a re...
Ichiro Mizunuma, Chia Shen, Morikazu Takegaki