3249 search results - page 440 / 650 » C Based Hardware Design for Wireless Applications |
179
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HYBRID
2005
Springer
16 years 1 days ago
2005
Springer
In this paper, we present a new design methodology for synchronous reactive systems, based on a clear separation between control and data flow parts. This methodology allows to fa...
188
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DATE
2007
IEEE
16 years 26 days ago
2007
IEEE
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formu...
143
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ISCA
1999
IEEE
15 years 10 months ago
1999
IEEE
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
175
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SIGOPS
2008
15 years 6 months ago
2008
The Caernarvon operating system was developed to demonstrate that a high assurance system for smart cards was technically feasible and commercially viable. The entire system has b...
187
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Publication
_2011.jpg "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision")
In this paper we present a scalable dataflow hard- ware architecture optimized for the computation of general- purpose vision algorithms—neuFlow—and a dataflow compiler—luaFl...