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DATE
2003
IEEE
96views Hardware» more  DATE 2003»
15 years 12 months ago
Test Data Compression: The System Integrator's Perspective
Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but al...
Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola N...
MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
15 years 5 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
INFOCOM
2006
IEEE
16 years 17 days ago
Optimizing Caching Policy for Loss Recovery in Reliable Multicast
— In reliable multicast, data packets can be cached at some nodes such as repair servers for future possible retransmission in loss recovery schemes. How to cache packets to opti...
Feng Xie, Gang Feng, Xun Yang
MOBICOM
2006
ACM
16 years 15 days ago
Analysis and implications of student contact patterns derived from campus schedules
Characterizing mobility or contact patterns in a campus environment is of interest for a variety of reasons. Existing studies of these patterns can be classified into two basic a...
Vikram Srinivasan, Mehul Motani, Wei Tsang Ooi
MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
15 years 10 months ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith