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WCNC
2008
IEEE
16 years 28 days ago
Two-Stage Code Acquisition Employing Search Space Reduction and Iterative Detection in the DS-UWB Downlink
— In this paper we propose and investigate an iterative code acquisition scheme assisted by both search space reduction and iterative Massage Passing (MP), which was designed for...
Seung Hwan Won, Lajos Hanzo
SIGCOMM
1996
ACM
15 years 10 months ago
Adaptive Resource Management Algorithms for Indoor Mobile Computing Environments
Emerging indoor mobile computing environments seek to provide a user with an advanced setofcommunication-intensive applications, which require sustained quality of service in the ...
Songwu Lu, Vaduvur Bharghavan
FPL
2006
Springer
105views Hardware» more  FPL 2006»
15 years 10 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...
VLSID
2006
IEEE
119views VLSI» more  VLSID 2006»
16 years 7 months ago
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core
Performance of applications can be boosted by executing application-specific Instruction Set Extensions (ISEs) on a specialized hardware coupled with a processor core. Many commer...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
16 years 3 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel