56 search results - page 9 / 12 » Buffering global interconnects in structured ASIC design |
169
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GLVLSI
2000
IEEE
15 years 10 months ago
2000
IEEE
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
160
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ASPDAC
2009
ACM
16 years 15 days ago
2009
ACM
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is pr...
156
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ICCAD
1997
IEEE
15 years 10 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
158
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
A tool that automates the floating-point to fixed-point conversion (FFC) process for digital signal processing systems is described. The tool automatically optimizes fixed-point d...
178
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DAC
2003
ACM
15 years 11 months ago
2003
ACM
In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem af...