37 search results - page 6 / 8 » Buffer Insertion for Noise and Delay Optimization |
142
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ISQED
2009
IEEE
16 years 26 days ago
2009
IEEE
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
152
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GLVLSI
2009
IEEE
16 years 24 days ago
2009
IEEE
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
161
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ISQED
2002
IEEE
15 years 11 months ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
157
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ICCAD
2001
IEEE
16 years 2 months ago
2001
IEEE
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating f...
172
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DAC
2011
ACM
14 years 5 months ago
2011
ACM
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significan...