-- This paper presents an efficient method for the timing verification of concurrent systems, modeled as labeled Timed Petri nets. The verification problems we consider require us ...
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP pro...
In this paper we present an analysis of the minimal hardware precision required to implement Support Vector Machine (SVM) classification within a Logarithmic Number System archite...
Faisal M. Khan, Mark G. Arnold, William M. Potteng...
This paper presents a new approach to understand the event stream model. Additionally a new approximation algorithm for the feasibility test of the sporadic and the generalized mu...
Many numerical schemes can be suitably studied from a system theoretic point of view. This paper studies the relationship between the two disciplines, that is, numerical analysis ...