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» Bounded-lifetime integrated circuits
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ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
16 years 12 hour ago
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
ITC
2003
IEEE
148views Hardware» more  ITC 2003»
15 years 11 months ago
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk
As technology evolves into the deep sub-micron era, signal integrity problems are growing into a major challenge. An important source of signal integrity problems is the crosstalk...
Xiaoliang Bai, Sujit Dey, Angela Krstic
3DIC
2009
IEEE
263views Hardware» more  3DIC 2009»
15 years 9 months ago
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...
Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwa...
DAC
2009
ACM
16 years 7 months ago
The day Sherlock Holmes decided to do EDA
Semiconductor design companies are in a continuous search for design tools that address the ever increasing chip design complexity coupled with strict time-to-market schedules and...
Andreas G. Veneris, Sean Safarpour
DAC
2009
ACM
16 years 7 months ago
Nanoscale digital computation through percolation
In this study, we apply a novel synthesis technique for implementing robust digital computation in nanoscale lattices with random interconnects: percolation theory on random graph...
Mustafa Altun, Marc D. Riedel, Claudia Neuhauser