1343 search results - page 174 / 269 » Bounded-lifetime integrated circuits |
163
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ISPD
2003
ACM
15 years 11 months ago
2003
ACM
A block-level placement and routing scheme called Fishbone is presented. The routing uses a two-layer spine topology. The pin locations are configurable and restricted to certain ...
165
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DAC
2010
ACM
15 years 10 months ago
2010
ACM
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
192
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GLVLSI
2009
IEEE
15 years 10 months ago
2009
IEEE
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
188
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IPSN
2010
Springer
15 years 8 months ago
2010
Springer
In-network processing is recommended for many sensor network applications to reduce communication and improve energy efficiency. However, constraints on memory, speed, and energy ...
166
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TVLSI
2002
15 years 6 months ago
2002
Abstract--The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to pow...