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» Bounded-lifetime integrated circuits
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FPGA
2004
ACM
145views FPGA» more  FPGA 2004»
15 years 12 months ago
Exploration of pipelined FPGA interconnect structures
In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...
Akshay Sharma, Katherine Compton, Carl Ebeling, Sc...
SIGIR
2003
ACM
15 years 11 months ago
HAT: a hardware assisted TOP-DOC inverted index component
A novel Hardware Assisted Top-Doc (HAT) component is disclosed. HAT is an optimized content indexing device based on a modified inverted index structure. HAT accommodates patterns...
S. Kagan Agun, Ophir Frieder
DATE
2002
IEEE
89views Hardware» more  DATE 2002»
15 years 11 months ago
A Hierarchical Test Scheme for System-On-Chip Designs
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pi...
DAC
2000
ACM
15 years 11 months ago
Fast power grid simulation
The decrease in feature size and added chip functionality in large sub-micron integrated circuits demand larger grids for power distribution. Since power grids are performance lim...
Sani R. Nassif, Joseph N. Kozhaya

Lab
782views
17 years 6 months ago
Neural Systems Engineering Lab (NSEL)
Neural Systems Engineering Lab (NSEL) at Michigan State University focuses on advancing neuroinformatics science by engineering new theoretical, computational and experimental tool...