1343 search results - page 162 / 269 » Bounded-lifetime integrated circuits |
161
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GLVLSI
2009
IEEE
16 years 1 months ago
2009
IEEE
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
183
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ISLPED
2009
ACM
16 years 1 months ago
2009
ACM
In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45 nm node. We demonstrate by circuit simulation and analytical model...
135
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ISCAS
2008
IEEE
16 years 27 days ago
2008
IEEE
— A precision integrated bandgap voltage reference in 0.35μm CMOS technology is here presented. The circuit uses natural npn bipolar transistors as reference diodes. A particula...
169
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DATE
2007
IEEE
16 years 26 days ago
2007
IEEE
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
170
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GLVLSI
2007
IEEE
16 years 25 days ago
2007
IEEE
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...