Sciweavers

1343 search results - page 161 / 269
» Bounded-lifetime integrated circuits
Sort
View
ICCAD
2003
IEEE
140views Hardware» more  ICCAD 2003»
16 years 3 months ago
Block-based Static Timing Analysis with Uncertainty
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
Anirudh Devgan, Chandramouli V. Kashyap
ICCAD
2002
IEEE
87views Hardware» more  ICCAD 2002»
16 years 3 months ago
A novel framework for multilevel routing considering routability and performance
We propose in this paper a novel framework for multilevel routing considering both routability and performance. The two-stage multilevel framework consists of coarsening followed ...
Shih-Ping Lin, Yao-Wen Chang
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
16 years 3 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
ISPD
2010
ACM
205views Hardware» more  ISPD 2010»
16 years 1 months ago
Total sensitivity based dfm optimization of standard library cells
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. Ho...
Yongchan Ban, Savithri Sundareswaran, David Z. Pan
ISPD
2009
ACM
126views Hardware» more  ISPD 2009»
16 years 1 months ago
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven h...
Yifang Liu, Jiang Hu