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» Bounded-lifetime integrated circuits
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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
16 years 3 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
GLVLSI
2006
IEEE
119views VLSI» more  GLVLSI 2006»
16 years 16 days ago
Thermal analysis of a 3D die-stacked high-performance microprocessor
3-dimensional integrated circuit (3D IC) technology places circuit blocks in the vertical dimension in addition to the conventional horizontal plane. Compared to conventional plan...
Kiran Puttaswamy, Gabriel H. Loh
VLSID
2007
IEEE
149views VLSI» more  VLSID 2007»
16 years 6 months ago
Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes
Title of thesis: EFFICIENT AND ACCURATE STATISTICAL TIMING ANALYSIS FOR NON-LINEAR NON-GAUSSIAN VARIABILITY WITH INCREMENTAL ATTRIBUTES Ashish Dobhal, Master of Science, 2006 Thes...
Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava
ICIP
2008
IEEE
16 years 8 months ago
Inverse image problem of designing phase shifting masks in optical lithography
The continual shrinkage of minimum feature size in integrated circuit (IC) fabrication incurs more and more serious distortion in the optical lithography process, generating circu...
Stanley H. Chan, Edmund Y. Lam
DAC
2007
ACM
16 years 7 months ago
Physical Unclonable Functions for Device Authentication and Secret Key Generation
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that...
G. Edward Suh, Srinivas Devadas