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ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
16 years 15 days ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
CASES
2006
ACM
16 years 13 days ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
16 years 16 days ago
Integrated placement and skew optimization for rotary clocking
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C....
UIST
2006
ACM
16 years 12 days ago
Reflective physical prototyping through integrated design, test, and analysis
Prototyping is the pivotal activity that structures innovation, collaboration, and creativity in design. Prototypes embody design hypotheses and enable designers to test them. Fra...
Björn Hartmann, Scott R. Klemmer, Michael Ber...
DAC
1999
ACM
16 years 7 months ago
Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology
A 550MHz 64b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS [1]. Both th...
D. Allen, D. Behrends, B. Stanisic