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ISPD
1999
ACM
127views Hardware» more  ISPD 1999»
15 years 11 months ago
Buffer insertion for clock delay and skew minimization
 Buffer insertion is an effective approach to achieve both minimal clock signal delay and skew in high speed VLSI circuit design. In this paper, we develop an optimal buffer ins...
X. Zeng, D. Zhou, Wei Li
EWC
2010
91views more  EWC 2010»
15 years 5 months ago
Multiobjective global surrogate modeling, dealing with the 5-percent problem
When dealing with computationally expensive simulation codes or process measurement data, surrogate modeling methods are firmly established as facilitators for design space explor...
Dirk Gorissen, Ivo Couckuyt, Eric Laermans, Tom Dh...
ICCAD
2000
IEEE
119views Hardware» more  ICCAD 2000»
15 years 11 months ago
Synthesis of Operation-Centric Hardware Descriptions
Most hardware description frameworks, whether schematic or textual, use cooperating finite state machines (CFSM) as the underlying abstraction. In the CFSM framework, a designer ...
James C. Hoe, Arvind
TC
2008
15 years 6 months ago
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
Assaf Shacham, Keren Bergman, Luca P. Carloni
ASE
2004
108views more  ASE 2004»
15 years 6 months ago
CODEWEAVE: Exploring Fine-Grained Mobility of Code
er is concerned with an abstract exploration of code mobility constructs designed for use in settings where the level of granularity associated with the mobile units exhibits sign...
Cecilia Mascolo, Gian Pietro Picco, Gruia-Catalin ...