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VLSID
2010
IEEE
155views VLSI» more  VLSID 2010»
15 years 4 months ago
Synchronized Generation of Directed Tests Using Satisfiability Solving
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
Xiaoke Qin, Mingsong Chen, Prabhat Mishra
AEI
2008
108views more  AEI 2008»
15 years 6 months ago
Combinatorial synthesis approach employing graph networks
The paper proposes a methodology to assist the designer at the initial stages of the design synthesis process by enabling him/her to employ knowledge and algorithms existing in gr...
Offer Shai, Noel Titus, Karthik Ramani
IFIP
2001
Springer
15 years 11 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
ASPLOS
2006
ACM
15 years 10 months ago
Accurate and efficient regression modeling for microarchitectural performance and power prediction
We propose regression modeling as an efficient approach for accurately predicting performance and power for various applications executing on any microprocessor configuration in a...
Benjamin C. Lee, David M. Brooks
JCISE
2002
128views more  JCISE 2002»
15 years 6 months ago
A Collaborative Framework for Integrated Part and Assembly Modeling
An ideal product modeling system should support both part modeling and assembly modeling, instead of just either of them as is the case in most current CAD systems. A good basis f...
Rafael Bidarra, Niels Kranendonk, Alex Noort, Will...