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DATE
2000
IEEE
142views Hardware» more  DATE 2000»
15 years 11 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
DATE
2000
IEEE
114views Hardware» more  DATE 2000»
15 years 11 months ago
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths
Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation who...
Michael Münch, Norbert Wehn, Bernd Wurth, Ren...
DATE
2000
IEEE
94views Hardware» more  DATE 2000»
15 years 11 months ago
Shared Memory Implementations of Synchronous Dataflow Specifications
There has been a proliferation of block-diagram environments for specifying and prototyping DSP systems. These include tools from academia like Ptolemy [3], and GRAPE [7], and com...
Praveen K. Murthy, Shuvra S. Bhattacharyya
179
Voted
DSN
2000
IEEE
15 years 11 months ago
Exploiting Non-Determinism for Reliability of Mobile Agent Systems
An important technical hurdle blocking the adoption of mobile agent technology is the lack of reliability. Designing a reliable mobile agent system is especially challenging since...
Ajay Mohindra, Apratim Purakayastha, Prasannaa Tha...
EH
2000
IEEE
183views Hardware» more  EH 2000»
15 years 11 months ago
A Reconfigurable Platform for the Automatic Synthesis of Analog Circuits
Reconfigurable chips are integrated circuits whose internal connections can be programmed by the user to attend a specific application. Field Programmable Gate Arrays (FPGAs) and ...
Ricardo Salem Zebulum, Cristina Costa Santini, Hel...