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DATE
2003
IEEE
131views Hardware» more  DATE 2003»
16 years 2 days ago
High Speed and Highly Testable Parallel Two-Rail Code Checker
In this article we propose a high speed and highly testable parallel two-rail code checker, which features a compact structure and is Totally-Self-Checking or Strongly Code-Disjoi...
Martin Omaña, Daniele Rossi, Cecilia Metra
DSN
2003
IEEE
16 years 2 days ago
Comparison of Failure Detectors and Group Membership: Performance Study of Two Atomic Broadcast Algorithms
Protocols that solve agreement problems are essential building blocks for fault tolerant distributed systems. While many protocols have been published, little has been done to ana...
Péter Urbán, Ilya Shnayderman, Andr&...
EH
2003
IEEE
117views Hardware» more  EH 2003»
16 years 2 days ago
The Evolutionary Design and Synthesis of Non-Linear Digital VLSI Systems
This paper describes a multi-objective Evolutionary Algorithm (EA) system for the synthesis of efficient non-linear VLSI circuit modules. The EA takes the specification for a no...
Robert Thomson, Tughrul Arslan
GLVLSI
2003
IEEE
175views VLSI» more  GLVLSI 2003»
16 years 2 days ago
A custom FPGA for the simulation of gene regulatory networks
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
Ilias Tagkopoulos, Charles A. Zukowski, German Cav...
HICSS
2003
IEEE
99views Biometrics» more  HICSS 2003»
16 years 2 days ago
Towards Feasible Topology Formation Algorithms for Bluetooth-based WPANs
In this paper, we tackle the problem of topology formation in Bluetooth Wireless Personal Area Networks (BTWPANs). We first overview and extend a previously proposed centralized ...
Carla-Fabiana Chiasserini, Marco Ajmone Marsan, El...