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ICCD
2008
IEEE
117views Hardware» more  ICCD 2008»
16 years 3 months ago
Two dimensional highly associative level-two cache design
High associativity is important for level-two cache designs [9]. Implementing CAM-based Highly Associative Caches (CAM-HAC), however, is both costly in hardware and exhibits poor s...
Chuanjun Zhang, Bing Xue
ICCD
2008
IEEE
111views Hardware» more  ICCD 2008»
16 years 3 months ago
Power switch characterization for fine-grained dynamic voltage scaling
—Dynamic voltage scaling (DVS) provides power savings for systems with varying performance requirements. One low overhead implementation of DVS uses PMOS power switches to connec...
Liang Di, Mateja Putic, John Lach, Benton H. Calho...
ICCAD
2008
IEEE
99views Hardware» more  ICCAD 2008»
16 years 3 months ago
Evaluation of voltage interpolation to address process variations
Abstract— Post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. ...
Kevin Brownell, Gu-Yeon Wei, David Brooks
ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
16 years 3 months ago
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Abstract— Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a us...
Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan ...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
16 years 3 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He