Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsc...
The results of fast implementations of all five AES final candidates using Virtex Xilinx Field Programmable Gate Arrays are presented and analyzed. Performance of several alternati...
Abstract. Modes of operation adapt block ciphers to many applications. Among the encryption modes, only CFB Cipher Feedback has both of the following properties: Firstly it allow...
Ammar Alkassar, Alexander Geraldy, Birgit Pfitzman...
Abstract: This paper introduces a new method for optimally provisioning and pricing differentiated services, that maximizes profit and maintains a small blocking probability. Reso...