Sciweavers

6404 search results - page 281 / 1281
» Blocks
Sort
View
ICPP
2002
IEEE
15 years 11 months ago
Out-of-Order Instruction Fetch Using Multiple Sequencers
Conventional instruction fetch mechanisms fetch contiguous blocks of instructions in each cycle. They are difficult to scale since taken branches make it hard to increase the siz...
Paramjit S. Oberoi, Gurindar S. Sohi
ICDT
2001
ACM
116views Database» more  ICDT 2001»
15 years 11 months ago
On Optimizing Nearest Neighbor Queries in High-Dimensional Data Spaces
Abstract. Nearest-neighbor queries in high-dimensional space are of high importance in various applications, especially in content-based indexing of multimedia data. For an optimiz...
Stefan Berchtold, Christian Böhm, Daniel A. K...
ICCAD
1999
IEEE
89views Hardware» more  ICCAD 1999»
15 years 11 months ago
A bipartition-codec architecture to reduce power in pipelined circuits
This paper proposes a new bipatition-codec architecture that may reduce power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of ...
Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-J...
FPGA
1997
ACM
127views FPGA» more  FPGA 1997»
15 years 10 months ago
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
Amit Chowdhary, John P. Hayes
DAC
1996
ACM
15 years 10 months ago
Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures
In this paper we address the problem of code generation for basic blocks in heterogeneous memory-register DSP processors. We propose a new a technique, based on register-transfer ...
Guido Araujo, Sharad Malik, Mike Tien-Chien Lee