Sciweavers

6404 search results - page 268 / 1281
» Blocks
Sort
View
FCCM
2006
IEEE
125views VLSI» more  FCCM 2006»
16 years 17 days ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St...
AICCSA
2005
IEEE
91views Hardware» more  AICCSA 2005»
16 years 4 days ago
Secure transmission of sensitive data using multiple channels
A new scheme for transmitting sensitive data is proposed, the proposed scheme depends on partitioning the output of a block encryption module using the Chinese Remainder Theorem a...
Abdelhamid S. Abdelhamid, Ahmed A. Belal
FCCM
2005
IEEE
111views VLSI» more  FCCM 2005»
16 years 4 days ago
A High-Performance Asynchronous FPGA: Test Results
We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC’s 0.18μm CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic ...
David Fang, John Teifel, Rajit Manohar
PPAM
2005
Springer
16 years 11 hour ago
Adapting Linear Algebra Codes to the Memory Hierarchy Using a Hypermatrix Scheme
Abstract. We present the way in which we adapt data and computations to the underlying memory hierarchy by means of a hierarchical data structure known as hypermatrix. The applicat...
José R. Herrero, Juan J. Navarro
ITC
2003
IEEE
113views Hardware» more  ITC 2003»
15 years 11 months ago
Fault Injection for Verifying Testability at the VHDL Level
This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allow...
S. R. Seward, Parag K. Lala