Sciweavers

6404 search results - page 153 / 1281
» Blocks
Sort
View
IJCES
2002
100views more  IJCES 2002»
15 years 6 months ago
Neural Network Decoders for Linear Block Codes
This paper presents a class of neural networks suitable for the application of decoding error-correcting codes.The neural model is basically a perceptron with a high-order polynom...
Ja-Ling Wu, Yuen-Hsien Tseng, Yuh-Ming Huang
DT
1998
85views more  DT 1998»
15 years 6 months ago
How Much Logic Should Go in an FPGA Logic Block?
The logic blocks of most modern FPGAs contain clusters of look-up tables and flip flops, yet little is known about good choices for several key architectural parameters related ...
Vaughn Betz, Jonathan Rose
VLSISP
2002
103views more  VLSISP 2002»
15 years 6 months ago
A New Class of Efficient Block-Iterative Interference Cancellation Techniques for Digital Communication Receivers
A new and efficient class of nonlinear receivers is introduced for digital communication systems. These "iterated-decision" receivers use optimized multipass algorithms t...
Albert M. Chan, Gregory W. Wornell
TSP
2008
118views more  TSP 2008»
15 years 5 months ago
A Block Component Model-Based Blind DS-CDMA Receiver
In this paper, we consider the problem of blind multiuser separation-equalization in the uplink of a wideband DS-CDMA system, in a multipath propagation environment with intersymbo...
Dimitri Nion, Lieven De Lathauwer
VTC
2010
IEEE
130views Communications» more  VTC 2010»
15 years 4 months ago
Performance of the Space-Time Block Coded DS-CDMA Uplink Employing Soft-Output ACO-Aided Multiuser Space-Time Detection and Iter
Abstract—In this treatise we propose a three-stage twin-transmitantenna assisted MultiUser (MU) Direct Sequence Code-Division Mulitple Access (DS-CDMA) system employing both a Un...
Chong Xu, Mohammed El-Hajjar, Robert G. Maunder, L...