This paper discusses a methodology used on an industrial hardware development project to validate various cache-coherence protocol components. The idea is to use a high level model...
Jesse D. Bingham, John Erickson, Gaurav Singh, Fle...
Efforts are underway to make it possible for a single operator to effectively control multiple robots. In these high workload situations, many questions arise including how many r...
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traff...
To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both ...
Abstract. In this paper we describe the OnEQL system, a query engine that implements optimization techniques and evaluation strategies to speed up the evaluation time of querying a...