Sciweavers

1159 search results - page 128 / 232
» Binary Decision Graphs
Sort
View
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
16 years 11 days ago
A fast logic simulator using a look up table cascade emulator
— This paper shows a new type of a cycle-based logic simulation method using a Look-Up Table (LUT) cascade emulator. The method first transforms a given circuit into LUT cascade...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
ACSD
2005
IEEE
71views Hardware» more  ACSD 2005»
16 years 12 hour ago
Maximal Causality Analysis
Perfectly synchronous systems immediately react to the inputs of their environment, which may lead to so-called causality cycles between actions and their trigger conditions. Algo...
Klaus Schneider, Jens Brandt, Tobias Schüle, ...
EDCC
2005
Springer
15 years 12 months ago
Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs
Abstract. Current paper proposes an efficient alternative for traditional gatelevel fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSB...
Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jut...
DATE
2002
IEEE
94views Hardware» more  DATE 2002»
15 years 11 months ago
Exact Grading of Multiple Path Delay Faults
The problem of fault grading for multiple path delay faults is studied and a method of obtaining the exact coverage is presented. The faults covered are represented and manipulate...
Saravanan Padmanaban, Spyros Tragoudas
TACAS
2001
Springer
92views Algorithms» more  TACAS 2001»
15 years 10 months ago
Language Containment Checking with Nondeterministic BDDs
Abstract. Checking for language containment between nondeterministic ω-automata is a central task in automata-based hierarchical verification. We present a symbolic procedure for...
Bernd Finkbeiner