This paper introduces S.P.L.O.T., a Web-based reasoning and configuration system for Software Product Lines (SPLs). The system benefits from mature logic-based reasoning techniq...
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...
— An exact closed-form expression is derived for the average bit-error probability (BEP) of binary phase-shift keying signals with multiple-antenna reception. We consider maximal...
We present quantum query complexity bounds for testing algebraic properties. For a set S and a binary operation on S, we consider the decision problem whether S is a semigroup or ...
— Reduced ordered Binary Decision Diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synt...